The present invention relates to a data transfer control unit for transferring data between two systems. More particularly, the invention relates to data transfer control for serial data transfer.
FIG. 4 shows a block diagram of two data transfer control units 1, 1A, each for performing serial data transfer. Control units 1, 1A show systems respectfully performing their operation under any different CPU. A data signal line 2 is used to conduct serial communication between the two systems. A control signal line 3 is used to control the communication.
The system of FIG. 4 also includes CPUs 4, 4A, and ROMs 5, 5A, which hold a program dedicated for running control units 1, 1A. RAMs 6, 6A hold programs and data during operation in addition to the program to be held in ROMs 5, 5A. Serial input/output (I/O) interfaces 7, 7A are used to perform communication between systems 1. 1A. Other I/O interfaces 8, 9 are used to connect peripheral equipment such as a keyboard and a CRT. System buses 10, 10A are used to send out address signals, data signals, and control signals such that CPUs 4, 4A will be connected by serial I/O interfaces 7, 7A.
The operation of the system of FIG. 4 will now be explained. Control units 1, 1A are capable of stand-alone operation according to the programs which are held in ROMs 5, 5A. CPUs 4, 4A load the program from ROMs 5, 5A of the other CPU through system buses 10, 10A. These programs are written in RAMs 6, 6A as needed during execution of the program. In addition, the states of I/O interfaces 8, 9 are monitored via system buses 10. 10A which are processing in response to each state. When exchanges of information are required between systems 1, 1A CPUs 4, 4A will exchange the information through serial I/O interfaces 7, 7A.
When information from one system is to be transferred to the other system, CPU 4 begins checking the feasibility of transmitting from the serial I/O interface 7. In case transmission cannot be accomplished, CPU 4 waits until the system is ready. When the system is ready the opposing CPU is signaled by the CPU of the first control unit on control line 3. The control signal is transmitted to the opposing CPU at serial I/O interface 7.
Serial I/O interface 7 receives the command from CPU 4 and outputs the data on data signal line 2. When serial I/O interface 7A of the other system 1A receives the data, it either informs CPU 4A that data signals are to be interrupted by means of interrupt signals or sets the internal flag. Once CPU 4A has received an interrupt signal or an internal flag has been set. CPU 4A reads the information from system 1 by means of serial I/O interface 7A. This information will be held in RAM 6A for later processing.
In case a plurality of data is sent, this process is repeated. Additionally, the sending of data from system 1A to system 1 will follow the same procedure.
The traditional data transfer is completed as discussed above. During data transfer CPUs 4, 4A of each system 1, 1A will be unavailable for processing information received by I/O interfaces 8, 9 of each system. As a result, the time required for effecting communication between the systems incorporating serial I/O interfaces 7, 7A can become quite substantial. In performing large quantities of data information exchange there have been problems loading host CPUs to the extent that large processing capability is required for CPUs 4, 4A.